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| Features * High Performance, Low Power AVR (R) 8-bit Microcontroller * Advanced RISC Architecture - 129 Powerful Instructions - Most Single Clock Cycle Execution - 32 x 8 General Purpose Working Registers - Fully Static Operation - Up to 1 MIPS throughput per MHz - On-chip 2-cycle Multiplier Data and Non-Volatile Program Memory - 8K Bytes Flash of In-System Programmable Program Memory * Endurance: 10,000 Write/Erase Cycles - Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write Operation - 512 Bytes of In-System Programmable EEPROM Endurance: 100,000 Write/Erase Cycles - 512 Bytes Internal SRAM - Programming Lock for Flash Program and EEPROM Data Security On Chip Debug Interface (debugWIRE) Peripheral Features - Two or three 12-bit High Speed PSC (Power Stage Controllers) with 4-bit Resolution Enhancement * Non Overlapping Inverted PWM Output Pins With Flexible Dead-Time * Variable PWM duty Cycle and Frequency * Synchronous Update of all PWM Registers * Auto Stop Function for Event Driven PFC Implementation * Less than 25 Hz Step Width at 150 kHz Output Frequency * PSC2 with four Output Pins and Output Matrix - One 8-bit General purpose Timer/Counter with Separate Prescaler and Capture Mode - One 16-bit General purpose Timer/Counter with Separate Prescaler, Compare Mode and Capture Mode - Programmable Serial USART * Standard UART mode * 16/17 bit Biphase Mode for DALI Communications - Master/Slave SPI Serial Interface - 10-bit ADC * Up To 11 Single Ended Channels and 2 Fully Differential ADC Channel Pairs * Programmable Gain (5x, 10x, 20x, 40x on Differential Channels) * Internal Reference Voltage - 10-bit DAC - Two or three Analog Comparator with Resistor-Array to Adjust Comparison Voltage - 4 External Interrupts - Programmable Watchdog Timer with Separate On-Chip Oscillator Special Microcontroller Features - Low Power Idle, Noise Reduction, and Power Down Modes - Power On Reset and Programmable Brown Out Detection - Flag Array in Bit-programmable I/O Space (4 bytes) * * * * * * 8-bit Microcontroller with 8K Bytes In-System Programmable Flash AT90PWM2 AT90PWM3 AT90PWM2B AT90PWM3B Summary * 4317IS-AVR-01/08 - In-System Programmable via SPI Port - Internal Calibrated RC Oscillator ( 8 MHz) - On-chip PLL for fast PWM ( 32 MHz, 64 MHz) and CPU (16 MHz) * Operating Voltage: 2.7V - 5.5V * Extended Operating Temperature: - -40 to +105 C Product AT90PWM2 AT90PWM2B AT90PWM3 AT90PWM3B Package SO24 SO32, QFN32 12 bit PWM with deadtime 2x2 3x2 ADC Input 8 11 ADC Diff 1 2 Analog Compar 2 3 Application One fluorescent ballast HID ballast, fluorescent ballast, Motor control 1. History Product AT90PWM2 AT90PWM3 Revision First revision of parts, only for running production. Second revision of parts, for all new developments. The major changes are : * complement the PSCOUT01, PSCOUT11, PSCOUT21 polarity in centered mode - See "PSCn0 & PSCn1 Basic Waveforms in Center Aligned Mode" on page 139. AT90PWM2B AT90PWM3B * Add the PSC software triggering capture - See "PSC 0 Input Capture Register - PICR0H and PICR0L" on page 170. * Add bits to read the PSC output activity - See "PSC0 Interrupt Flag Register - PIFR0" on page 172. * Add some clock configurations - See "Device Clocking Options Select AT90PWM2B/3B" on page 31. * Change Amplifier Synchonization - See "Amplifier" on page 252. and See "" on page 254. * Correction of the Errata - See "Errata" on page 23. This datasheet deals with product characteristics of AT90PW2 and AT90WM3. It will be updated as soon as characterization will be done. 2. Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized. 2 AT90PWM2/3/2B/3B 4317IS-AVR-01/08 AT90PWM2/3/2B/3B 3. Pin Configurations Figure 3-1. SOIC 24-pin Package AT90PWM2/2B SOIC24 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 PB7(ADC4/PSCOUT01/SCK) PB6 (ADC7/ICP1B) PB5 (ADC6/INT2) PB4 (AMP0+) PB3 (AMP0-) AREF GND AVCC PB2 (ADC5/INT1) PD7 (ACMP0) PD6 (ADC3/ACMPM/INT0) PD5 (ADC2/ACMP2) (PSCOUT00/XCK/SS_A) PD0 (RESET/OCD) PE0 (PSCIN0/CLKO) PD1 (PSCIN2/OC1A/MISO_A) PD2 (TXD/DALI/OC0A/SS/MOSI_A) PD3 VCC GND (MISO/PSCOUT20) PB0 (MOSI/PSCOUT21) PB1 (OC0B/XTAL1) PE1 (ADC0/XTAL2) PE2 (ADC1/RXD/DALI/ICP1A/SCK_A) PD4 Figure 3-2. SOIC 32-pin Package AT90PWM3/3B SOIC 32 (PSCOUT00/XCK/SS_A) PD0 (INT3/PSCOUT10) PC0 (RESET/OCD) PE0 (PSCIN0/CLKO) PD1 (PSCIN2/OC1A/MISO_A) PD2 (TXD/DALI/OC0A/SS/MOSI_A) PD3 (PSCIN1/OC1B) PC1 VCC GND (T0/PSCOUT22) PC2 (T1/PSCOUT23) PC3 (MISO/PSCOUT20) PB0 (MOSI/PSCOUT21) PB1 (OC0B/XTAL1) PE1 (ADC0/XTAL2) PE2 (ADC1/RXD/DALI/ICP1A/SCK_A) PD4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 PB7(ADC4/PSCOUT01/SCK) PB6 (ADC7/PSCOUT11/ICP1B) PB5 (ADC6/INT2) PC7 (D2A) PB4 (AMP0+) PB3 (AMP0-) PC6 (ADC10/ACMP1) AREF GND AVCC PC5 (ADC9/AMP1+) PC4 (ADC8/AMP1-) PB2 (ADC5/INT1) PD7 (ACMP0) PD6 (ADC3/ACMPM/INT0) PD5 (ADC2/ACMP2) 3 4317IS-AVR-01/08 Figure 3-3. QFN32 (7*7 mm) Package. AT90PWM3/3B QFN 32 PD0 (PSCOUT00/XCK/SS_A) PB7 (ADC4/PSCOUT01/SCK) PB6 (ADC7/PSCOUT11/ICP1B) PB5 (ADC6/INT2) PC7 (D2A) PD1(PSCIN0/CLKO) 32 31 30 29 28 27 26 25 PE0 (RESET/OCD) PC0(INT3/PSCOUT10) (PSCIN2/OC1A/MISO_A) PD2 (TXD/DALI/OC0A/SS/MOSI_A) PD3 (PSCIN1/OC1B) PC1 VCC GND (T0/PSCOUT22) PC2 (T1/PSCOUT23) PC3 (MISO/PSCOUT20) PB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 PB4 (AMP0+) PB3 (AMP0-) PC6 (ADC10/ACMP1) AREF AGND AVCC PC5 (ADC9/AMP1+) PC4 (ADC8/AMP1-) 3.1 Pin Descriptions : Table 3-1. S024 Pin Number 7 18 Pin out description SO32 Pin Number 9 24 QFN32 Pin Number 5 20 Mnemonic GND AGND Type Power Power Name, Function & Alternate Function Ground: 0V reference Analog Ground: 0V reference for analog part 4 AT90PWM2/3/2B/3B 4317IS-AVR-01/08 (MOSI/PSCOUT21) PB1 (OC0B/XTAL1) PE1 (ADC0/XTAL2) PE2 (ADC1/RXD/DALI/ICP1_A/SCK_A) PD4 (ADC2/ACMP2 ) PD5 (ADC3/ACMPM/INT0) PD6 (ACMP0) PD7 (ADC5/INT1) PB2 AT90PWM2/3/2B/3B Table 3-1. S024 Pin Number 6 Pin out description (Continued) SO32 Pin Number 8 QFN32 Pin Number 4 Mnemonic VCC Type power Name, Function & Alternate Function Power Supply: Analog Power Supply: This is the power supply voltage for analog part For a normal use this pin must be connected. Analog Reference : reference for analog converter . This is the reference voltage of the A/D converter. As output, can be used by external analog MISO (SPI Master In Slave Out) PSCOUT20 output MOSI (SPI Master Out Slave In) PSCOUT21 output ADC5 (Analog Input Channel5 ) INT1 AMP0- (Analog Differential Amplifier 0 Input Channel ) AMP0+ (Analog Differential Amplifier 0 Input Channel ) ADC6 (Analog Input Channel 6) INT 2 ADC7 (Analog Input Channel 7) 17 23 19 AVCC Power 19 25 21 AREF Power 8 12 8 PBO I/O 9 13 9 PB1 I/O 16 20 21 22 20 27 28 30 16 23 24 26 PB2 PB3 PB4 PB5 I/O I/O I/O I/O 23 31 27 PB6 I/O ICP1B (Timer 1 input capture alternate input) PSCOUT11 output (see note 1) PSCOUT01 output 24 32 28 PB7 I/O ADC4 (Analog Input Channel 4) SCK (SPI Clock) 2 30 PC0 I/O PSCOUT10 output (see note 1) INT3 PSCIN1 (PSC 1 Digital Input) OC1B (Timer 1 Output Compare B) T0 (Timer 0 clock input) PSCOUT22 output T1 (Timer 1 clock input) PSCOUT23 output ADC8 (Analog Input Channel 8) AMP1- (Analog Differential Amplifier 1 Input Channel ) 7 3 PC1 I/O 10 6 PC2 I/O 11 NA 21 7 PC3 I/O I/O 17 PC4 22 18 PC5 I/O ADC9 (Analog Input Channel 9) AMP1+ (Analog Differential Amplifier 1 Input Channel ) ADC10 (Analog Input Channel 10) ACMP1 (Analog Comparator 1 Positive Input ) D2A : DAC output 26 29 22 25 PC6 PC7 I/O I/O 5 4317IS-AVR-01/08 Table 3-1. S024 Pin Number Pin out description (Continued) SO32 Pin Number QFN32 Pin Number Mnemonic Type Name, Function & Alternate Function PSCOUT00 output 1 1 29 PD0 I/O XCK (UART Transfer Clock) SS_A (Alternate SPI Slave Select) 3 4 32 PD1 I/O PSCIN0 (PSC 0 Digital Input ) CLKO (System Clock Output) PSCIN2 (PSC 2 Digital Input) 4 5 1 PD2 I/O OC1A (Timer 1 Output Compare A) MISO_A (Programming & alternate SPI Master In Slave Out) TXD (Dali/UART Tx data) 5 6 2 PD3 I/O OC0A (Timer 0 Output Compare A) SS (SPI Slave Select) MOSI_A (Programming & alternate Master Out SPI Slave In) ADC1 (Analog Input Channel 1) 12 16 12 PD4 I/O RXD (Dali/UART Rx data) ICP1A (Timer 1 input capture) SCK_A (Programming & alternate SPI Clock) 13 17 13 PD5 I/O ADC2 (Analog Input Channel 2) ACMP2 (Analog Comparator 2 Positive Input ) ADC3 (Analog Input Channel 3 ) 14 18 14 PD6 I/O ACMPM reference for analog comparators INT0 15 2 19 3 15 31 PD7 PE0 I/O I/O or I ACMP0 (Analog Comparator 0 Positive Input ) RESET (Reset Input) OCD (On Chip Debug I/O) XTAL1: XTAL Input OC0B (Timer 0 Output Compare B) XTAL2: XTAL OuTput ADC0 (Analog Input Channel 0) 10 14 10 PE1 I/O 11 15 11 PE2 I/O 1. PSCOUT10 & PSCOUT11 are not present on 24 pins package 4. Overview The AT90PWM2/2B/3/3B is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the AT90PWM2/2B/3/3B achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 6 AT90PWM2/3/2B/3B 4317IS-AVR-01/08 AT90PWM2/3/2B/3B 4.1 Block Diagram Figure 4-1. Block Diagram Data Bus 8-bit 8Kx8 Flash Program Memory Program Counter Status and Control Interrupt Unit SPI Unit Instruction Register 32 x 8 General Purpose Registrers Watchdog Timer 3 Analog Comparators Indirect Addressing Instruction Decoder Direct Addressing ALU DALI USART Control Lines Timer 0 Timer 1 Data SRAM 512 bytes ADC EEPROM 512 bytes DAC I/O Lines PSC 2/1/0 The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The AT90PWM2/2B/3/3B provides the following features: 8K bytes of In-System Programmable Flash with Read-While-Write capabilities, 512 bytes EEPROM, 512 bytes SRAM, 53 general purpose I/O lines, 32 general purpose working registers,three Power Stage Controllers, two flexible Timer/Counters with compare modes and PWM, one USART with DALI mode, an 11channel 10-bit ADC with two differential input stage with programmable gain, a 10-bit DAC, a programmable Watchdog Timer with Internal Oscillator, an SPI serial port, an On-chip Debug system and four software selectable power saving modes. 7 4317IS-AVR-01/08 The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI ports and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize switching noise during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. The device is manufactured using Atmel's high-density nonvolatile memory technology. The Onchip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel AT90PWM2/3 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The AT90PWM2/3 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. 4.2 4.2.1 Pin Descriptions VCC Digital supply voltage. 4.2.2 GND Ground. 4.2.3 Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the AT90PWM2/2B/3/3B as listed on page 69. 4.2.4 Port C (PC7..PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port C is not available on 24 pins package. Port C also serves the functions of special features of the AT90PWM2/2B/3/3B as listed on page 71. 8 AT90PWM2/3/2B/3B 4317IS-AVR-01/08 AT90PWM2/3/2B/3B 4.2.5 Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the AT90PWM2/2B/3/3B as listed on page 74. 4.2.6 Port E (PE2..0) RESET/ XTAL1/ XTAL2 Port E is an 3-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the RSTDISBL Fuse is programmed, PE0 is used as an I/O pin. Note that the electrical characteristics of PE0 differ from those of the other pins of Port C. If the RSTDISBL Fuse is unprogrammed, PE0 is used as a Reset input. A low level on this pin for longer than the minimum pulse length will generate a Reset, even if the clock is not running. The minimum pulse length is given in Table 9-1 on page 47. Shorter pulses are not guaranteed to generate a Reset. Depending on the clock selection fuse settings, PE1 can be used as input to the inverting Oscillator amplifier and input to the internal clock operating circuit. Depending on the clock selection fuse settings, PE2 can be used as output from the inverting Oscillator amplifier. The various special features of Port E are elaborated in "Alternate Functions of Port E" on page 77 and "Clock Systems and their Distribution" on page 29. 4.2.7 AVCC AVCC is the supply voltage pin for the A/D Converter. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a lowpass filter. 4.2.8 AREF This is the analog reference pin for the A/D Converter. 4.3 About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. 9 4317IS-AVR-01/08 5. Register Summary Address (0xFF) (0xFE) (0xFD) (0xFC) (0xFB) (0xFA) (0xF9) (0xF8) (0xF7) (0xF6) (0xF5) (0xF4) (0xF3) (0xF2) (0xF1) (0xF0) (0xEF) (0xEE) (0xED) (0xEC) (0xEB) (0xEA) (0xE9) (0xE8) (0xE7) (0xE6) (0xE5) (0xE4) (0xE3) (0xE2) (0xE1) (0xE0) (0xDF) (0xDE) (0xDD) (0xDC) (0xDB) (0xDA) (0xD9) (0xD8) (0xD7) (0xD6) (0xD5) (0xD4) (0xD3) (0xD2) (0xD1) (0xD0) (0xCF) (0xCE) (0xCD) (0xCC) (0xCB) (0xCA) (0xC9) (0xC8) (0xC7) (0xC6) (0xC5) (0xC4) (0xC3) (0xC2) (0xC1) (0xC0) (0xBF) Name PICR2H PICR2L PFRC2B PFRC2A PCTL2 PCNF2 OCR2RBH OCR2RBL OCR2SBH OCR2SBL OCR2RAH OCR2RAL OCR2SAH OCR2SAL POM2 PSOC2 PICR1H PICR1L PFRC1B PFRC1A PCTL1 PCNF1 OCR1RBH OCR1RBL OCR1SBH OCR1SBL OCR1RAH OCR1RAL OCR1SAH OCR1SAL Reserved PSOC1 PICR0H PICR0L PFRC0B PFRC0A PCTL0 PCNF0 OCR0RBH OCR0RBL OCR0SBH OCR0SBL OCR0RAH OCR0RAL OCR0SAH OCR0SAL Reserved PSOC0 Reserved EUDR MUBRRH MUBRRL Reserved EUCSRC EUCSRB EUCSRA Reserved UDR UBRRH UBRRL Reserved UCSRC UCSRB UCSRA Reserved Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page page 170 page 170 PCAE2B PCAE2A PPRE21 PFIFTY2 PISEL2B PISEL2A PPRE20 PALOCK2 PELEV2B PELEV2A PBFM2 PLOCK2 PFLTE2B PFLTE2A PAOC2B PMODE21 PRFM2B3 PRFM2A3 PAOC2A PMODE20 PRFM2B2 PRFM2A2 PARUN2 POP2 PRFM2B1 PRFM2A1 PCCYC2 PCLKSEL2 PRFM2B0 PRFM2A0 PRUN2 POME2 page 169 page 168 page 167 page 164 page 164 page 164 page 163 page 163 page 163 page 163 page 163 page 163 POMV2B3 POS23 POMV2B2 POS22 POMV2B1 PSYNC21 POMV2B0 PSYNC20 POMV2A3 POEN2D POMV2A2 POEN2B POMV2A1 POEN2C POMV2A0 POEN2A page 171 page 162 page 170 page 170 PCAE1B PCAE1A PPRE11 PFIFTY1 PISEL1B PISEL1A PPRE10 PALOCK1 PELEV1B PELEV1A PBFM1 PLOCK1 PFLTE1B PFLTE1A PAOC1B PMODE11 PRFM1B3 PRFM1A3 PAOC1A PMODE10 PRFM1B2 PRFM1A2 PARUN1 POP1 PRFM1B1 PRFM1A1 PCCYC1 PCLKSEL1 PRFM1B0 PRFM1A0 PRUN1 - page 169 page 168 page 166 page 164 page 164 page 164 page 163 page 163 page 163 page 163 page 163 page 163 - - - - - PSYNC11 - PSYNC10 - - - POEN1B - - - POEN1A page 162 page 170 page 170 PCAE0B PCAE0A PPRE01 PFIFTY0 PISEL0B PISEL0A PPRE00 PALOCK0 PELEV0B PELEV0A PBFM0 PLOCK0 PFLTE0B PFLTE0A PAOC0B PMODE01 PRFM0B3 PRFM0A3 PAOC0A PMODE00 PRFM0B2 PRFM0A2 PARUN0 POP0 PRFM0B1 PRFM0A1 PCCYC0 PCLKSEL0 PRFM0B0 PRFM0A0 PRUN0 - page 169 page 168 page 165 page 164 page 164 page 164 page 163 page 163 page 163 page 163 page 163 page 163 - - - EUDR7 MUBRR15 MUBRR7 - - - UTxS3 - UDR07 - UBRR07 - - RXCIE0 RXC0 - - - - EUDR6 MUBRR014 MUBRR6 - - - UTxS2 - UDR06 - UBRR06 - UMSEL0 TXCIE0 TXC0 - - PSYNC01 - EUDR5 MUBRR13 MUBRR5 - - - UTxS1 - UDR05 - UBRR05 - UPM01 UDRIE0 UDRE0 - - PSYNC00 - EUDR4 MUBRR12 MUBRR4 - - EUSART UTxS0 - UDR04 - UBRR04 - UPM00 RXEN0 FE0 - - - - EUDR3 MUBRR011 MUBRR3 - FEM EUSBS URxS3 - UDR03 UBRR011 UBRR03 - USBS0 TXEN0 DOR0 - - POEN0B - EUDR2 MUBRR010 MUBRR2 - F1617 - URxS2 - UDR02 UBRR010 UBRR02 - UCSZ01 UCSZ02 UPE0 - - - - EUDR1 MUBRR9 MUBRR1 - STP1 EMCH URxS1 - UDR01 UBRR09 UBRR01 - UCSZ00 RXB80 U2X0 - - POEN0A - EUDR0 MUBRR8 MUBRR0 - STP0 BODR URxS0 - UDR00 UBRR08 UBRR00 - UCPOL0 TXB80 MPCM0 - page 205 page 204 page 203 page 221 & page 202 page 207 page 207 page 225 page 224 page 223 page 221 page 226 page 226 page 162 10 AT90PWM2/3/2B/3B 4317IS-AVR-01/08 AT90PWM2/3/2B/3B Address (0xBE) (0xBD) (0xBC) (0xBB) (0xBA) (0xB9) (0xB8) (0xB7) (0xB6) (0xB5) (0xB4) (0xB3) (0xB2) (0xB1) (0xB0) (0xAF) (0xAE) (0xAD) (0xAC) (0xAB) (0xAA) (0xA9) (0xA8) (0xA7) (0xA6) (0xA5) (0xA4) (0xA3) (0xA2) (0xA1) (0xA0) (0x9F) (0x9E) (0x9D) (0x9C) (0x9B) (0x9A) (0x99) (0x98) (0x97) (0x96) (0x95) (0x94) (0x93) (0x92) (0x91) (0x90) (0x8F) (0x8E) (0x8D) (0x8C) (0x8B) (0x8A) (0x89) (0x88) (0x87) (0x86) (0x85) (0x84) (0x83) (0x82) (0x81) (0x80) (0x7F) (0x7E) (0x7D) Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved AC2CON AC1CON AC0CON DACH DACL DACON Reserved Reserved Reserved Reserved PIM2 PIFR2 PIM1 PIFR1 PIM0 PIFR0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved OCR1BH OCR1BL OCR1AH OCR1AL ICR1H ICR1L TCNT1H TCNT1L Reserved TCCR1C TCCR1B TCCR1A DIDR1 DIDR0 Reserved Bit 7 - - - - - - - - - - - - - - - AC2EN AC1EN AC0EN - / DAC9 DAC7 / DAC1 DAATE - - - - - - - - - - - - - - - - - - - - - - - - OCR1B15 OCR1B7 OCR1A15 OCR1A7 ICR115 ICR17 TCNT115 TCNT17 - FOC1A ICNC1 COM1A1 - ADC7D - Bit 6 - - - - - - - - - - - - - - - AC2IE AC1IE AC0IE - / DAC8 DAC6 /DAC0 DATS2 - - - - - - - - - - - - - - - - - - - - - - - - OCR1B14 OCR1B6 OCR1A14 OCR1A6 ICR114 ICR16 TCNT114 TCNT16 - FOC1B ICES1 COM1A0 - ADC6D - Bit 5 - - - - - - - - - - - - - - - AC2IS1 AC1IS1 AC0IS1 - / DAC7 DAC5 / DATS1 - - - - PSEIE2 PSEI2 PSEIE1 PSEI1 PSEIE0 PSEI0 - - - - - - - - - - - - - - - - - - - - OCR1B13 OCR1B5 OCR1A13 OCR1A5 ICR113 ICR15 TCNT113 TCNT15 - - - COM1B1 ACMP0D ADC5D - Bit 4 - - - - - - - - - - - - - - - AC2IS0 AC1IS0 AC0IS0 - / DAC6 DAC4 / DATS0 - - - - PEVE2B PEV2B PEVE1B PEV1B PEVE0B PEV0B - - - - - - - - - - - - - - - - - - - - OCR1B12 OCR1B4 OCR1A12 OCR1A4 ICR112 ICR14 TCNT112 TCNT14 - - WGM13 COM1B0 AMP0PD ADC4D - Bit 3 - - - - - - - - - - - - - - - AC2SADEAC1ICE - / DAC5 DAC3 / - - - - PEVE2A PEV2A PEVE1A PEV1A PEVE0A PEV0A - - - - - - - - - - - - - - - - - - - - OCR1B11 OCR1B3 OCR1A11 OCR1A3 ICR111 ICR13 TCNT111 TCNT13 - - WGM12 - AMP0ND ADC3D/ACMPMD - Bit 2 - - - - - - - - - - - - - - - AC2M2 AC1M2 AC0M2 - / DAC4 DAC2 / DALA - - - - PRN21 PRN11 PRN01 - - - - - - - - - - - - - - - - - - - - OCR1B10 OCR1B2 OCR1A10 OCR1A2 ICR110 ICR12 TCNT110 TCNT12 - - CS12 - ADC10D/ACMP1D ADC2D/ACMP2D - Bit 1 - - - - - - - - - - - - - - - AC2M1 AC1M1 AC0M1 DAC9 / DAC3 DAC1 / DAOE - - - - PRN20 PRN10 PRN00 - - - - - - - - - - - - - - - - - - - - OCR1B9 OCR1B1 OCR1A9 OCR1A1 ICR19 ICR11 TCNT19 TCNT11 - - CS11 WGM11 ADC9D/AMP1PD ADC1D - Bit 0 - - - - - - - - - - - - - - - AC2M0 AC1M0 AC0M0 DAC8 / DAC2 DAC0 / DAEN - - - - PEOPE2 PEOP2 PEOPE1 PEOP1 PEOPE0 PEOP0 - - - - - - - - - - - - - - - - - - - - OCR1B8 OCR1B0 OCR1A8 OCR1A0 ICR18 ICR10 TCNT18 TCNT10 - - CS10 WGM10 ADC8D/AMP1ND ADC0D - Page page 230 page 229 page 228 page 262 page 262 page 261 page 172 page 172 page 171 page 172 page 171 page 172 page 127 page 127 page 127 page 127 page 128 page 128 page 127 page 127 page 127 page 126 page 123 page 252 page 251 11 4317IS-AVR-01/08 Address (0x7C) (0x7B) (0x7A) (0x79) (0x78) (0x77) (0x76) (0x75) (0x74) (0x73) (0x72) (0x71) (0x70) (0x6F) (0x6E) (0x6D) (0x6C) (0x6B) (0x6A) (0x69) (0x68) (0x67) (0x66) (0x65) (0x64) (0x63) (0x62) (0x61) (0x60) 0x3F (0x5F) 0x3E (0x5E) 0x3D (0x5D) 0x3C (0x5C) 0x3B (0x5B) 0x3A (0x5A) 0x39 (0x59) 0x38 (0x58) 0x37 (0x57) 0x36 (0x56) 0x35 (0x55) 0x34 (0x54) 0x33 (0x53) 0x32 (0x52) 0x31 (0x51) 0x30 (0x50) 0x2F (0x4F) 0x2E (0x4E) 0x2D (0x4D) 0x2C (0x4C) 0x2B (0x4B) 0x2A (0x4A) 0x29 (0x49) 0x28 (0x48) 0x27 (0x47) 0x26 (0x46) 0x25 (0x45) 0x24 (0x44) 0x23 (0x43) 0x22 (0x42) 0x21 (0x41) 0x20 (0x40) 0x1F (0x3F) 0x1E (0x3E) 0x1D (0x3D) 0x1C (0x3C) 0x1B (0x3B) Name ADMUX ADCSRB ADCSRA ADCH ADCL AMP1CSR AMP0CSR Reserved Reserved Reserved Reserved Reserved Reserved TIMSK1 TIMSK0 Reserved Reserved Reserved Reserved EICRA Reserved Reserved OSCCAL Reserved PRR Reserved Reserved CLKPR WDTCSR SREG SPH SPL Reserved Reserved Reserved Reserved Reserved SPMCSR Reserved MCUCR MCUSR SMCR MSMCR MONDR ACSR Reserved SPDR SPSR SPCR Reserved Reserved PLLCSR OCR0B OCR0A TCNT0 TCCR0B TCCR0A GTCCR EEARH EEARL EEDR EECR GPIOR0 EIMSK EIFR GPIOR3 Bit 7 REFS1 ADHSM ADEN - / ADC9 ADC7 / ADC1 AMP1EN AMP0EN - - - - - - - - - - - - ISC31 - - - - PRPSC2 - - CLKPCE WDIF I SP15 SP7 - - - - - SPMIE - SPIPS - - Bit 6 REFS0 - ADSC - / ADC8 ADC6 / ADC0 - - - - - - - - - - - - ISC30 - - CAL6 - PRPSC1 - - - WDIE T SP14 SP6 - - - - - RWWSB - - - - Bit 5 ADLAR - ADATE - / ADC7 ADC5 / AMP1G1 AMP0G1 - - - - - - ICIE1 - - - - - ISC21 - - CAL5 - PRPSC0 - - - WDP3 H SP13 SP5 - - - - - - - - - - Bit 4 - ADASCR ADIF - / ADC6 ADC4 / AMP1G0 AMP0G0 - - - - - - - - - - - - ISC20 - - CAL4 - PRTIM1 - - - WDCE S SP12 SP4 - - - - - RWWSRE - PUD - - Bit 3 MUX3 ADTS3 ADIE - / ADC5 ADC3 / - - - - - - - - - - - - ISC11 - - CAL3 - PRTIM0 - - CLKPS3 WDE V SP11 SP3 - - - - - BLBSET - - WDRF SM2 Bit 2 MUX2 ADTS2 ADPS2 - / ADC4 ADC2 / AMP1TS2 AMP0TS2 - - - - - - OCIE1B OCIE0B - - - - ISC10 - - CAL2 - PRSPI - - CLKPS2 WDP2 N SP10 SP2 - - - - - PGWRT - - BORF SM1 Bit 1 MUX1 ADTS1 ADPS1 ADC9 / ADC3 ADC1 / AMP1TS1 AMP0TS1 - - - - - - OCIE1A OCIE0A - - - - ISC01 - - CAL1 - PRUSART - - CLKPS1 WDP1 Z SP9 SP1 - - - - - PGERS - IVSEL EXTRF SM0 Bit 0 MUX0 ADTS0 ADPS0 ADC8 / ADC2 ADC0 / AMP1TS0 AMP0TS0 - - - - - - TOIE1 TOIE0 - - - - ISC00 - - CAL0 - PRADC - - CLKPS0 WDP0 C SP8 SP0 - - - - - SPMEN - IVCE PORF SE Page page 247 page 249 page 248 page 251 page 251 page 257 page 256 page 128 page 101 page 81 page 34 page 43 page 39 page 54 page 13 page 15 page 15 page 271 page 60 & page 68 page 50 page 41 reserved reserved Monitor Stop Mode Control Register Monitor Data Register ACCKDIV - SPD7 SPIF SPIE - - OCR0B7 OCR0A7 TCNT07 FOC0A COM0A1 TSM - EEAR7 EEDR7 - GPIOR07 - - GPIOR37 AC2IF - SPD6 WCOL SPE - - OCR0B6 OCR0A6 TCNT06 FOC0B COM0A0 ICPSEL1 - EEAR6 EEDR6 - GPIOR06 - - GPIOR36 AC1IF - SPD5 - DORD - - OCR0B5 OCR0A5 TCNT05 - COM0B1 - - EEAR5 EEDR5 - GPIOR05 - - GPIOR35 AC0IF - SPD4 - MSTR - - OCR0B4 OCR0A4 TCNT04 - COM0B0 - - EEAR4 EEDR4 - GPIOR04 - - GPIOR34 - - SPD3 - CPOL - - OCR0B3 OCR0A3 TCNT03 WGM02 - - EEAR11 EEAR3 EEDR3 EERIE GPIOR03 INT3 INTF3 GPIOR33 AC2O - SPD2 - CPHA - - PLLF OCR0B2 OCR0A2 TCNT02 CS02 - - EEAR10 EEAR2 EEDR2 EEMWE GPIOR02 INT2 INTF2 GPIOR32 AC1O - SPD1 - SPR1 - - PLLE OCR0B1 OCR0A1 TCNT01 CS01 WGM01 - EEAR9 EEAR1 EEDR1 EEWE GPIOR01 INT1 INTF1 GPIOR31 AC0O - SPD0 SPI2X SPR0 - - PLOCK OCR0B0 OCR0A0 TCNT00 CS00 WGM00 PSRSYNC EEAR8 EEAR0 EEDR0 EERE GPIOR00 INT0 INTF0 GPIOR30 page 231 page 181 page 181 page 179 page 37 page 101 page 100 page 100 page 99 page 96 page 84 page 21 page 21 page 22 page 22 page 27 page 82 page 82 page 28 12 AT90PWM2/3/2B/3B 4317IS-AVR-01/08 AT90PWM2/3/2B/3B Address 0x1A (0x3A) 0x19 (0x39) 0x18 (0x38) 0x17 (0x37) 0x16 (0x36) 0x15 (0x35) 0x14 (0x34) 0x13 (0x33) 0x12 (0x32) 0x11 (0x31) 0x10 (0x30) 0x0F (0x2F) 0x0E (0x2E) 0x0D (0x2D) 0x0C (0x2C) 0x0B (0x2B) 0x0A (0x2A) 0x09 (0x29) 0x08 (0x28) 0x07 (0x27) 0x06 (0x26) 0x05 (0x25) 0x04 (0x24) 0x03 (0x23) 0x02 (0x22) 0x01 (0x21) 0x00 (0x20) Name GPIOR2 GPIOR1 Reserved Reserved TIFR1 TIFR0 Reserved Reserved Reserved Reserved Reserved Reserved PORTE DDRE PINE PORTD DDRD PIND PORTC DDRC PINC PORTB DDRB PINB Reserved Reserved Reserved Bit 7 GPIOR27 GPIOR17 - - - - - - - - - - - - - PORTD7 DDD7 PIND7 PORTC7 DDC7 PINC7 PORTB7 DDB7 PINB7 - - - Bit 6 GPIOR26 GPIOR16 - - - - - - - - - - - - - PORTD6 DDD6 PIND6 PORTC6 DDC6 PINC6 PORTB6 DDB6 PINB6 - - - Bit 5 GPIOR25 GPIOR15 - - ICF1 - - - - - - - - - - PORTD5 DDD5 PIND5 PORTC5 DDC5 PINC5 PORTB5 DDB5 PINB5 - - - Bit 4 GPIOR24 GPIOR14 - - - - - - - - - - - - - PORTD4 DDD4 PIND4 PORTC4 DDC4 PINC4 PORTB4 DDB4 PINB4 - - - Bit 3 GPIOR23 GPIOR13 - - - - - - - - - - - - - PORTD3 DDD3 PIND3 PORTC3 DDC3 PINC3 PORTB3 DDB3 PINB3 - - - Bit 2 GPIOR22 GPIOR12 - - OCF1B OCF0B - - - - - - PORTE2 DDE2 PINE2 PORTD2 DDD2 PIND2 PORTC2 DDC2 PINC2 PORTB2 DDB2 PINB2 - - - Bit 1 GPIOR21 GPIOR11 - - OCF1A OCF0A - - - - - - PORTE1 DDE1 PINE1 PORTD1 DDD1 PIND1 PORTC1 DDC1 PINC1 PORTB1 DDB1 PINB1 - - - Bit 0 GPIOR20 GPIOR10 - - TOV1 TOV0 - - - - - - PORTE0 DDE0 PINE0 PORTD0 DDD0 PIND0 PORTC0 DDC0 PINC0 PORTB0 DDB0 PINB0 - - - Page page 27 page 27 page 129 page 101 page 79 page 80 page 80 page 79 page 79 page 79 page 79 page 79 page 79 page 78 page 78 page 79 Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The AT90PWM2/2B/3/3B is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. 13 4317IS-AVR-01/08 6. Instruction Set Summary Mnemonics ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER MUL MULS MULSU FMUL FMULS FMULSU RJMP IJMP RCALL ICALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC BRIE BRID Rd,Rr Rd,Rr Rd,Rr Rd,K Rr, b Rr, b P, b P, b s, k s, k k k k k k k k k k k k k k k k k k k k Operands Rd, Rr Rd, Rr Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd,K Rd,K Rd Rd Rd Rd Rd Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr k Description Add two Registers Add with Carry two Registers Add Immediate to Word Subtract two Registers Subtract Constant from Register Subtract with Carry two Registers Subtract with Carry Constant from Reg. Subtract Immediate from Word Logical AND Registers Logical AND Register and Constant Logical OR Registers Logical OR Register and Constant Exclusive OR Registers One's Complement Two's Complement Set Bit(s) in Register Clear Bit(s) in Register Increment Decrement Test for Zero or Minus Clear Register Set Register Multiply Unsigned Multiply Signed Multiply Signed with Unsigned Fractional Multiply Unsigned Fractional Multiply Signed Fractional Multiply Signed with Unsigned BRANCH INSTRUCTIONS Relative Jump Indirect Jump to (Z) Relative Subroutine Call Indirect Call to (Z) Subroutine Return Interrupt Return Compare, Skip if Equal Compare Compare with Carry Compare Register with Immediate Skip if Bit in Register Cleared Skip if Bit in Register is Set Skip if Bit in I/O Register Cleared Skip if Bit in I/O Register is Set Branch if Status Flag Set Branch if Status Flag Cleared Branch if Equal Branch if Not Equal Branch if Carry Set Branch if Carry Cleared Branch if Same or Higher Branch if Lower Branch if Minus Branch if Plus Branch if Greater or Equal, Signed Branch if Less Than Zero, Signed Branch if Half Carry Flag Set Branch if Half Carry Flag Cleared Branch if T Flag Set Branch if T Flag Cleared Branch if Overflow Flag is Set Branch if Overflow Flag is Cleared Branch if Interrupt Enabled Branch if Interrupt Disabled Operation Rd Rd + Rr Rd Rd + Rr + C Rdh:Rdl Rdh:Rdl + K Rd Rd - Rr Rd Rd - K Rd Rd - Rr - C Rd Rd - K - C Rdh:Rdl Rdh:Rdl - K Rd Rd * Rr Rd Rd * K Rd Rd v Rr Rd Rd v K Rd Rd Rr Rd 0xFF - Rd Rd 0x00 - Rd Rd Rd v K Rd Rd * (0xFF - K) Rd Rd + 1 Rd Rd - 1 Rd Rd * Rd Rd Rd Rd Rd 0xFF R1:R0 Rd x Rr R1:R0 Rd x Rr R1:R0 Rd x Rr R1:R0 (Rd x Rr) << 1 R1:R0 (Rd x Rr) << 1 R1:R0 (Rd x Rr) << 1 PC PC + k + 1 PC Z PC PC + k + 1 PC Z PC STACK PC STACK if (Rd = Rr) PC PC + 2 or 3 Rd - Rr Rd - Rr - C Rd - K if (Rr(b)=0) PC PC + 2 or 3 if (Rr(b)=1) PC PC + 2 or 3 if (P(b)=0) PC PC + 2 or 3 if (P(b)=1) PC PC + 2 or 3 if (SREG(s) = 1) then PCPC+k + 1 if (SREG(s) = 0) then PCPC+k + 1 if (Z = 1) then PC PC + k + 1 if (Z = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (N = 1) then PC PC + k + 1 if (N = 0) then PC PC + k + 1 if (N V= 0) then PC PC + k + 1 if (N V= 1) then PC PC + k + 1 if (H = 1) then PC PC + k + 1 if (H = 0) then PC PC + k + 1 if (T = 1) then PC PC + k + 1 if (T = 0) then PC PC + k + 1 if (V = 1) then PC PC + k + 1 if (V = 0) then PC PC + k + 1 if ( I = 1) then PC PC + k + 1 if ( I = 0) then PC PC + k + 1 Flags Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None Z,C Z,C Z,C Z,C Z,C Z,C None None None None None I None Z, N,V,C,H Z, N,V,C,H Z, N,V,C,H None None None None None None None None None None None None None None None None None None None None None None None None #Clocks 1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 3 3 4 4 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 ARITHMETIC AND LOGIC INSTRUCTIONS 14 AT90PWM2/3/2B/3B 4317IS-AVR-01/08 AT90PWM2/3/2B/3B Mnemonics SBI CBI LSL LSR ROL ROR ASR SWAP BSET BCLR BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH MOV MOVW LDI LD LD LD LD LD LD LDD LD LD LD LDD LDS ST ST ST ST ST ST STD ST ST ST STD STS LPM LPM LPM SPM IN OUT PUSH POP Rd, P P, Rr Rr Rd Rd, Z Rd, Z+ Rd, Rr Rd, Rr Rd, K Rd, X Rd, X+ Rd, - X Rd, Y Rd, Y+ Rd, - Y Rd,Y+q Rd, Z Rd, Z+ Rd, -Z Rd, Z+q Rd, k X, Rr X+, Rr - X, Rr Y, Rr Y+, Rr - Y, Rr Y+q,Rr Z, Rr Z+, Rr -Z, Rr Z+q,Rr k, Rr Operands P,b P,b Rd Rd Rd Rd Rd Rd s s Rr, b Rd, b Description Set Bit in I/O Register Clear Bit in I/O Register Logical Shift Left Logical Shift Right Rotate Left Through Carry Rotate Right Through Carry Arithmetic Shift Right Swap Nibbles Flag Set Flag Clear Bit Store from Register to T Bit load from T to Register Set Carry Clear Carry Set Negative Flag Clear Negative Flag Set Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Set Signed Test Flag Clear Signed Test Flag Set Twos Complement Overflow. Clear Twos Complement Overflow Set T in SREG Clear T in SREG Set Half Carry Flag in SREG Clear Half Carry Flag in SREG Operation I/O(P,b) 1 I/O(P,b) 0 Rd(n+1) Rd(n), Rd(0) 0 Rd(n) Rd(n+1), Rd(7) 0 Rd(0)C,Rd(n+1) Rd(n),CRd(7) Rd(7)C,Rd(n) Rd(n+1),CRd(0) Rd(n) Rd(n+1), n=0..6 Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0) SREG(s) 1 SREG(s) 0 T Rr(b) Rd(b) T C1 C0 N1 N0 Z1 Z0 I1 I0 S1 S0 V1 V0 T1 T0 H1 H0 Rd Rr Rd+1:Rd Rr+1:Rr Rd K Rd (X) Rd (X), X X + 1 X X - 1, Rd (X) Rd (Y) Rd (Y), Y Y + 1 Y Y - 1, Rd (Y) Rd (Y + q) Rd (Z) Rd (Z), Z Z+1 Z Z - 1, Rd (Z) Rd (Z + q) Rd (k) (X) Rr (X) Rr, X X + 1 X X - 1, (X) Rr (Y) Rr (Y) Rr, Y Y + 1 Y Y - 1, (Y) Rr (Y + q) Rr (Z) Rr (Z) Rr, Z Z + 1 Z Z - 1, (Z) Rr (Z + q) Rr (k) Rr R0 (Z) Rd (Z) Rd (Z), Z Z+1 (Z) R1:R0 Rd P P Rr STACK Rr Rd STACK Flags None None Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V None SREG(s) SREG(s) T None C C N N Z Z I I S S V V T T H H None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None #Clocks 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 1 1 2 2 BIT AND BIT-TEST INSTRUCTIONS DATA TRANSFER INSTRUCTIONS Move Between Registers Copy Register Word Load Immediate Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Direct from SRAM Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Direct to SRAM Load Program Memory Load Program Memory Load Program Memory and Post-Inc Store Program Memory In Port Out Port Push Register on Stack Pop Register from Stack MCU CONTROL INSTRUCTIONS 15 4317IS-AVR-01/08 Mnemonics NOP SLEEP WDR BREAK Operands Description No Operation Sleep Watchdog Reset Break Operation (see specific descr. for Sleep function) (see specific descr. for WDR/timer) For On-chip Debug Only Flags None None None None #Clocks 1 1 1 N/A 16 AT90PWM2/3/2B/3B 4317IS-AVR-01/08 AT90PWM2/3/2B/3B 7. Ordering Information Speed (MHz) 16 16 16 16 16 16 16 16 16 Note: Note: Note: Note: Note: Power Supply 2.7 - 5.5V 2.7 - 5.5V 2.7 - 5.5V 2.7 - 5.5V 2.7 - 5.5V 2.7 - 5.5V 2.7 - 5.5V 2.7 - 5.5V 2.7 - 5.5V Ordering Code AT90PWM3-16SQ AT90PWM3-16MQT AT90PWM2-16SQ AT90PWM3B-16SE AT90PWM3B-16ME AT90PWM2B-16SE AT90PWM3B-16SU AT90PWM3B-16MU AT90PWM2B-16SU Package SO32 QFN32 SO24 SO32 QFN32 SO24 SO32 QFN32 SO24 Operation Range Extended (-40C to 105C) Extended (-40C to 105C) Extended (-40C to 105C) Engineering Samples Engineering Samples Engineering Samples Extended (-40C to 105C) Extended (-40C to 105C) Extended (-40C to 105C) All packages are Pb free, fully LHF This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. Parts numbers are for shipping in sticks (SO) or in trays (QFN). Thes devices can also be supplied in Tape and Reel. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. PWM2 is not recommended for new designs, use PWM2B for your developments PWM3 is not recommended for new designs, use PWM3B for your developments 17 4317IS-AVR-01/08 8. Package Information Package Type SO24 SO32 QFN32 24-Lead, Small Outline Package 32-Lead, Small Outline Package 32-Lead, Quad Flat No lead 18 AT90PWM2/3/2B/3B 4317IS-AVR-01/08 AT90PWM2/3/2B/3B 8.1 SO24 19 4317IS-AVR-01/08 8.2 SO32 20 AT90PWM2/3/2B/3B 4317IS-AVR-01/08 AT90PWM2/3/2B/3B 8.3 QFN32 21 4317IS-AVR-01/08 22 AT90PWM2/3/2B/3B 4317IS-AVR-01/08 AT90PWM2/3/2B/3B 9. Errata 9.1 AT90PWM2&3 Rev. A (Mask Revision) * * * * * * * * * * * * * * * * * PGM: PSCxRB Fuse PSC: Prescaler PSC: PAOCnA and PAOCnB Register Bits (Asynchronous output control) PSC: PEVxA/B Flag Bits PSC: Output Polarity in Centered Mode PSC: Output Activity VREF DALI DAC: Register Update DAC: Output spikes DAC driver: Output Voltage linearity ADC: Conversion accuracy Analog comparator: Offset value Analog comparator: Output signal PSC: Autolock modes DALI: 17th bit detection PSC: One ramp mode with PSC input mode 8 1. PGM: PSCnRB Fuse The use of PSCnRB fuse can make the parallel ISP fail. Workaround: When PSCnRB fuses are used, use the serial programming mode to load a new program version. 2. PSC: Prescaler The use of PSC's prescaler have the following effects : It blocks the sample of PSC inputs until the two first cycles following the set of PSC run bit. A fault is not properly transferred to other (slave) PSC. Workaround: Clear the prescaler PPREx bit when stopping the PSC (prun = 0), and set them to appropriate value when starting the PSC (prun = 1), these bits are in the same PCTL register Do not use the prescaler when a fault on one PSC should affect other PSC's 3. PSC: PAOCnA and PAOCnB Register Bits (Asynchronous output control) These register bits are malfunctioning. Workaround: Do not use this feature. 4. PSC: PEVnA/B flag bits These flags are set when a fault arises, but can also be set again during the fault itself. Workaround: Don't clear these flags before the fault disappears. 23 4317IS-AVR-01/08 5. PSC: Output Polarity in Centered Mode In centered mode, PSCOUTn1 outputs are not inverted, so they are active at the same time as PSCOUTn0. Workaround: Use an external inverter (or a driver with inverting output) to drive the load on PSCOUTn1. 6. PSC : POACnA/B Output Activity These register bits are not implemented in rev A. Workaround: Do not use this feature. 7. VREF Remark: To have Internal Vref on AREF pin select an internal analog feature such as DAC or ADC. Some stand by power consuption may be observed if Vref equals AVcc 8. DALI Some troubles on Dali extension when edges are not symmetric. Workaround: Use an optocoupler providing symmetric edges on Rx and Tx DALI lines (only recommanded for software validation purpose). 9. DAC: Register Update Registers DACL & DACH are not written when the DAC is not enabled. Workaround: Enable DAC with DAEN before writing in DACL & DACH. To prevent an unwanted zero output on DAC pin, enable DAC output, with DAOE afterwards. 10. DAC : Output spikes During transition between two codes, a spike may appears Work around: Filter spike or wait for steady state No spike appears if the 4 last signifiant bits remain zero. 11. DAC driver: Output Voltage linearity The voltage linearity of the DAC driver is limited when the DAC output goes above Vcc - 1V. Work around: Do not use AVcc as Vref ; internal Vref gives good results 12. ADC : Conversion accuracy The conversion accuracy degrades when the ADC clock is 1 & 2 MHz. Work around: When a 10 bit conversion accuracy is required, use an ADC clock of 500 kHz or below. 13. Analog comparator: Offset value The offset value increases when the common mode voltage is above Vcc - 1.5V. Work around: Limit common mode voltage 14. Analog comparator: Output signal 24 AT90PWM2/3/2B/3B 4317IS-AVR-01/08 AT90PWM2/3/2B/3B The comparator output toggles at the comparator clock frequency when the voltage difference between both inputs is lower than the offset. This may occur when comparing signal with small slew rate. Work around: This effect normally do not impact the PSC, as the transition is sampled once per PSC cycle Be carefull when using the comparator as an interrupt source. 15. PSC : Autolock mode This mode is not properly handled when CLKPSC is different from CLK IO. Work around: With CLKPSC equals 64/32 MHz (CLKPLL), use LOCK mode 16. DALI : 17th bit detection 17th bit detection do not occurs if the signal arrives after the sampling point. Workaround: Use this feature only for sofware development and not in field conditions 17. PSC : One ramp mode with PSC input mode 8 The retriggering is not properly handled in this case. Work around: Do not program this case. 18. PSC : Desactivation of outputs in mode 14 See "PSC Input Mode 14: Fixed Frequency Edge Retrigger PSC and Disactivate Output" on page 155. Work around: Do not use this mode to desactivate output if retrigger event do not occurs during On-Time. 9.2 AT90PWM2B/3B * * PSC : Double End-Of-Cycle Interrupt Request in Centered Mode ADC : Conversion accuracy In centered mode, after the "expected" End-Of-Cycle Interrupt, a second unexpected Interrupt occurs 1 PSC cycle after the previous interrupt. Work around: While CPU cycle is lower than PSC clock, the CPU sees only one interrupt request. For PSC clock period greater than CPU cycle, the second interrupt request must be cleared by software. 2. ADC : Conversion accuracy The conversion accuracy degrades when the ADC clock is 2 MHz. Work around: When a 10 bit conversion accuracy is required, use an ADC clock of 1 MHz or below. At 2 Mhz the ADC can be used as a 7 bits ADC. 3. DAC Driver linearity above 3.6V With 5V Vcc, the DAC driver linearity is poor when DAC output level is above Vcc-1V. At 5V, DAC output for 1023 will be around 5V - 40mV. Work around: . 25 1. PSC : Double End-Of-Cycle Interrupt Request in Centered Mode 4317IS-AVR-01/08 Use, when Vcc=5V, Vref below Vcc-1V. Or, when Vref=Vcc=5V, do not uses codes above 800. 4. DAC Update in Autotrig mode If the cpu writes in DACH register at the same instant that the selected trigger source occurs and DAC Auto Trigger is enabled, the DACH register is not updated by the new value. Work around: . When using the autotrig mode, write twice in the DACH register. The time between the two CPU writes, must be different than the trigger source frequency. 26 AT90PWM2/3/2B/3B 4317IS-AVR-01/08 AT90PWM2/3/2B/3B 10. Datasheet Revision History for AT90PWM2/2B/3/3B Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 10.1 Changes from 4317A- to 4317B 1. PSC section has been rewritten. 2. Suppression of description of RAMPZ which does not exist. 10.2 Changes from 4317B- to 4317C 1. Added AT90PWM2B/3B Advance Information. 2. Various updates throughout the document. 10.3 Changes from 4317C- to 4317D 1. Update of Electrical and Typical Characteristics. 10.4 Changes from 4317D to 4317E 1. Changed product status from "Advanced Information" to "Preliminary". 10.5 Changes from 4317E to 4317F 1. Remove JMP and CALL instruction in the Instruction Set Summary 2. Daisy chain of PSC input is only done in mode 7 - See "Fault events in Autorun mode" on page 160. 3. Updated "Output Compare SA Register - OCRnSAH and OCRnSAL" on page 163 4. Updated "Output Compare RA Register - OCRnRAH and OCRnRAL" on page 163 5. Updated "Output Compare SB Register - OCRnSBH and OCRnSBL" on page 163 6. Updated "Output Compare RB Register - OCRnRBH and OCRnRBL" on page 164 7. Specify the "Analog Comparator Propagation Delay" - See "DC Characteristics" on page 300. 8. Specify the "Reset Characteristics" - See "Reset Characteristics(1)" on page 47. 9. Specify the "Brown-out Characteristics" - See "Brown-out Characteristics(1)" on page 49. 10. Specify the "Internal Voltage Reference Characteristics - See "Internal Voltage Reference Characteristics(1)" on page 51. 10.6 Changes from 4317F to 4317G 1. Describe the amplifier operation for Rev B. 2. Clarify the fact that the DAC load given is the worst case. 3. Specify the ADC Min and Max clock frequency. 4. Describe the retrigger mode 8 in one ramp mode. 5. Specify that the amplifier only provides a 8 bits accuracy. 10.7 Changes from 4317G to 4317H 1. Updated "History" on page 2 2. Specify the "AREF Voltage vs. Temperature" on page 329 27 4317IS-AVR-01/08 3. PSC : the Balance Flank Width Modulation is done On-Time 1 rather than On-Time 0 (correction of figures) 4. Updated "Maximum Speed vs. VCC" on page 303 (formulas are removed) 5. Update of the "Errata" on page 23 10.8 Changes from 4317H to 4317I 1. Updated "History" on page 2 2. Updated "Device Clocking Options Select AT90PWM2B/3B" on page 31 3. Updated "Start-up Times when the PLL is selected as system clock" on page 35 4. Updated "ADC Noise Canceler" on page 241 5. Updated "ADC Auto Trigger Source Selection for non amplified conversions" on page 250. 6. Added "ADC Auto Trigger Source Selection for amplified conversions" on page 250 7. Updated "Amplifier" on page 252 8. Updated "Amplifier 0 Control and Status register - AMP0CSR" on page 256 9. Updated "AMP0 Auto Trigger Source Selection" on page 257 10. Updated "Amplifier 1Control and Status register - AMP1CSR" on page 257 11. Updated "AMP1 Auto Trigger source selection" on page 258 12. Updated DAC "Features" on page 259 (Output Impedance) 13. Updated temperature range in "DC Characteristics" on page 300 14. Updated Vhysr in "DC Characteristics" on page 300 15. Updated "ADC Characteristics" on page 306 16. Updated "Example 1" on page 315 17. Updated "Example 2" on page 315 18. Updated "Example 3" on page 316 19. Added "I/O Pin Input HysteresisVoltage vs. VCC" on page 322 20. Updated "Ordering Information" on page 17 21. Added Errata for "AT90PWM2B/3B" on page 25 22. Updated Package Drawings "Package Information" on page 18. 23. Updated table on page 2. 24. Updated "Calibrated Internal RC Oscillator" on page 33. 25. Added "Calibrated Internal RC Oscillator Accuracy" on page 302. 26. Updated Figure 27-35 on page 329. 27. Updated Figure 27-36 on page 330. 28. Updated Figure 27-37 on page 330. 28 AT90PWM2/3/2B/3B 4317IS-AVR-01/08 Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 International Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Product Contact Web Site www.atmel.com Technical Support Enter Product Line E-mail Sales Contact www.atmel.com/contacts Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL'S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL'S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel's products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. (c) 2008 Atmel Corporation. All rights reserved. Atmel (R), logo and combinations thereof, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. 4317IS-AVR-01/08 |
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